The invention relates to the field of redundancy in systems. More specifically, the invention relates to enabling redundancy in Peripheral Component Interconnect Express (PCI-Express) architecture in a data processing system.
PCI architecture typically enables communication between a plurality of peripheral devices and a host in a data processing system. The host detects and initializes the peripheral devices on the data processing system and enables communication between the peripheral devices.
In conventional data processing systems, the PCI architecture used is a shared bus topology, providing lanes for communication between the peripheral devices and the host. A PCI bus (PCI or PCI-X) is used to enable the shared bus topology. The PCI bus is a parallel multiplexed address/data/control bus, with either 32-bit or 64-bit data paths. However, in current data processing systems, the PCI-Express architecture uses a point-to-point topology, in which a switch replaces the bus as the single shared resource by means of which the peripheral devices communicate. Unlike a shared bus topology, where the peripheral devices collectively arbitrate among themselves for the use of the bus, each peripheral device in a point-to-point topology has direct and exclusive access to the switch. PCI-Express is therefore a serialized version of the PCI bus, with standard PCI-Express transactions being encoded into packets that are transmitted serially in a single-bit stream.
In embedded applications such as network appliances, routers or telecom equipment, the reliability of PCI-Express is a concern, since there is no provision for redundancy; for example, if the switch fails, the data processing system also fails.
Further, in current data processing systems, communication between the peripheral devices fails when no host is operational. Even communication between peripheral devices with processors fails, when no host is operational.
In light of the above discussion, there is a need for a system that provides a robust PCI-Express architecture. This system should provide redundancy when the host or the switch is not operational, to improve the reliability of the PCI-Express architecture. Further, the system should enable communication between—peripheral devices as well as external access to the system, when no host is operational.